Kien Tran-Hoang
Hanoi
Summary
As a passionate and innovative Cybersecurity Researcher, I am actively seeking opportunities to contribute to a dynamic and challenging environment. With a great passion and outstanding achievements in researching the Post-Quantum Cryptography, I am committed to bringing broad knowledge and in-depth skills in both hardware and software domains. My strong understanding of computer architectures as well as cryptographic architectures and flexible proficiency in programming languages such as C/C++ and Verilog are aspects I take pride in.
With enthusiasm and dedication, I aspire to advance my career and contribute to building groundbreaking products and services in the field of cryptographic systems.
Overview
1
1
year of professional experience
1
1
Certification
Work History
ASIC Design Engineer (Part-time)
Hitachi Industry & Control Solutions, Ltd
Tokyo, Japan
08.2025 - Current
(Caravel–OpenLane–Pulpissimo ASIC Project)
- Design an automated ASIC design flow for generating SoCs based on the Pulpissimo platform, integrating the designed SoCs into Caravel, and performing the ASIC process using the OpenLane platform.
- Write guideline documentation for this integrated workflow.
- Make a comparison between the use of the open-source platforms and commercial (license-required) alternatives.
Teaching Assistant
Tokyo University of Agriculture and Technology
Tokyo, Japan
04.2025 - Current
- Assisted mainly in VLSI & Hardware Design class for the Professor, such as preparing instructional materials, mentoring undergraduate students, grading assignments.
- Helped with grading assignments and tests, providing constructive feedback to students based on results.
Cryptographer (Internship)
Toshiba Corporation
Kawasaki, Japan
08.2025 - 09.2025
(Digital Signature Post-Quantum Cryptography Falcon Accelerator Project)
- Increased the Falcon's software processing speed by optimizing the Reduction Algorithm for Modular Multiplication in software.
- Implemented with liboqs (OQS) library.
- Analyzed the processing speed of Falcon software with different environments (ARM cores, Intel cores).
Education
Master of Engineering - Electrical Engineering And Computer Science
Tokyo University of Agriculture And Technology
Tokyo10-2026
Bachelor of Engineering - Electronics And Telecommunications Engineering
Hanoi University of Science And Technology
Hanoi, Vietnam04-2024
Certification
NAKAJO Laboratory - Master Student (Sep 2024 - Present)
Research mainly on Post-Quantum Cryptography CRYSTALS-Kyber Cryptosystem for low-cost embedded devices.
- Design an cryptosystem in both hardware and software sides.
- Optimized the NTT/INTT process, the polynomial multiplication operation, hash function, memory usage in hardware.
- Optimized the software code by using vector-friendly library.
- Enhanced the security ability for the memory.
EDABK Laboratory - Bachelor Student (Sep 2023 - April 2024)
Research mainly on System on Chip (SoC) Integration for low-cost embedded devices.
- Designed the SoC integrated Convolutional Accelerator to accelerate the image compression process with the real-time data from camera.
- Researched on the itegration of RISC-V Multi-core SoC for the Handwritten-digit Recognition Accelerator.
Timeline
ASIC Design Engineer (Part-time)
Hitachi Industry & Control Solutions, Ltd
08.2025 - Current
Cryptographer (Internship)
Toshiba Corporation
08.2025 - 09.2025
Teaching Assistant
Tokyo University of Agriculture and Technology
04.2025 - Current
Master of Engineering - Electrical Engineering And Computer Science
Tokyo University of Agriculture And Technology
Bachelor of Engineering - Electronics And Telecommunications Engineering
Hanoi University of Science And Technology
Publication & Awards
- Kien Tran-Hoang, Hironori Nakajo “A Study of Multi-Core CRYSTALS-Kyber Accelerator Based on a RISC-V Processor,” RECONF (Reconfigurable Systems), IEICE Hot Spring Annual Meeting, 2025.
- Kien Tran-Hoang, Hironori Nakajo, “Hardware/Software Co-Design for a Multi-Core Post-Quantum Cryptography CRYSTALS-Kyber Accelerator," In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'25), CSCE 2025, in press (2026).
- Kien Tran-Hoang, Hironori Nakajo, “Kyress: A Secure, Scalable, and Resource-Efficient CRYSTALS-Kyber Cryptosystem for Low-Cost Embedded Devices,” The Journal of Supercomputing (Springer), in press (2026).
- The third prize Award of LSI Design Contest in Okinawa, Japan, 2024.
- JASSO Scholarship for the exchange program in Japan, 2023.
- Japanese Government (MEXT) Scholarship, 2024.
- Nitori International Scholarship, 2025.
Relevant Skills
- Languages: English – Proficient in verbal communication; fluent in technical reading and academic writing.
Japanese – JLPT N3. - Strong independent analytical thinking and problem-solving abilities in research environments.
- Comfortable working in international research environments and collaborating with cross-cultural teams.
- Highly motivated to continuously learn and quickly adapt to new technologies and emerging research topics.