Hoang Gia Thang
Design Verification Engineer
Ho Chi Minh City,SG
Summary
Accomplished Design Verification Engineer with SystemVerilog expertise, skilled in assertion-based verification. Proven ability in streamlining testing processes, leading projects, and mentoring teams to enhance product reliability.
Overview
1
1
Language
5
5
years of professional experience
Work History
Design Verification Engineer
Renesas Design Vietnam
Ho Chi Minh City, Ho Chi Minh
04.2021 - Current
- Crafted and deployed test plans for SubSystem, Peripheral IPs (UART, SPI, I2C, I3C) of company product strengthening product reliability.
- Led design verification projects to ensure compliance with specifications and standards.
- Streamlined verification processes, enhancing efficiency in testing workflows and documentation.
- Conducted root cause analysis on defects, implementing corrective actions for continuous improvement.
- Mentored junior engineers on verification techniques and best practices in the design process.
- Interfaced with bus protocols in Gen 5 SoCs for automotive, constructing UVM scenarios to evaluate error detection performance.
- Utilized company in-house tools and environments for operational efficiency
- Implemented sets of scripts for workflow automation, aiding team productivity.
Education
Bachelor of Science - Electrical, Electronics And Communications Engineering
Ho Chi Minh City University of Technology
Ho Chi Minh City, Vietnam 04.2001 -
Skills
Assertion-based verification
SystemVerilog expertise
Hardware-software co-verification
Scripting languages
RTL design expertise
Timeline
Design Verification Engineer
Renesas Design Vietnam
04.2021 - Current
Bachelor of Science - Electrical, Electronics And Communications Engineering
Ho Chi Minh City University of Technology
04.2001 -